Charge coupled solid state imaging devices can be used to produce video images. The resolution of such an image can be increased by reducing the pixel size of such a device thus increasing the number of pixels per unit area. The reduction of the pixel size, however, may result in the following problems. First, it may be difficult to maintain the charge handling capacity as the size of a vertical charge coupled device (CCD) is reduced. Second, an image smear may increase as the distance between the photodiode and the vertical charge coupled device is decreased. Third, a dark current may reduce the signal-to-noise ratio because the signal may deteriorate as the area of the photodiode decreases.
A solid state imaging device has a photodiode array which photoelectrically converts incident light into electrical signals. Vertical and horizontal charge coupled devices transfer the electrical signals generated by the photodiode array, and an output circuit amplifies the output signal and converts the amplified signal to a voltage signal. The signal photoelectrically converted from the photodiode is transferred to the vertical charge coupled device during a vertical blanking interval and transmitted to the horizontal charge coupled device step by step during a horizontal blanking interval. The charge transmitted to the horizontal charge coupled device is transferred to a floating diffusion amplifier. This signal is photoelectrically converted from the photodiode and transmitted to the vertical charge coupled device through a transmission gate responsive to a gate bias signal of a field shift voltage.
Typically, the transmission gate is provided between the photodiode and the vertical charge coupled device. Before the field shift voltage is applied, the transmission gate is doped with a p-type dopant to form a potential barrier between the photodiode and the vertical charge coupled device. The transmission gate is doped with a sufficiently low dopant concentration to not form a hole accumulation layer. Because the silicon boundary of the transmission gate region does not have a hole accumulation layer, electrons generated from the silicon boundary may flow to the photodiode and to the vertical charge coupled device mixing with the signal charge thereby creating the dark current.
FIG. 1 illustrates a pixel structure for a solid state imaging device according to the prior art. This pixel structure includes a p-type well 12 having a low dopant concentration formed in an n-type substrate 10 having a low dopant concentration. An n-type well 14 of intermediate dopant concentration is formed on the p-type well 12, and a p-type well 16 of intermediate dopant concentration is formed on the n-type well 14 at a charge transfer region of the pixel. An n-type charge coupled region 22 having a relatively high dopant concentration is formed on the p-type well 16, and this n-type charge coupled region 22 provides a vertical charge coupled device (VCCD).
A gate insulation layer 24 is provided on the surface of the substrate 10, and the gate electrode 26 is formed on the charge transfer region of the substrate. An n-type photodiode region 18 is formed on the n-type well 14 at a light receiving region of the pixel, and this n-type photodiode region is self-aligned with the gate electrode layer 26. This n-type photodiode region provides an n-type photoelectric conversion region. A p-type channel stop region 19 having a relatively high dopant concentration and a p-type hole accumulation 20 having a high dopant concentration are formed. The gate electrode layer 26 is covered with an insulation layer 28, and a light shielding layer 30 is formed on the insulation layer 28. A passivation layer 32 is formed on the light shielding layer 30.
In the pixel structure illustrated in FIG. 1, a charge generated at the photoelectric conversion region 18 is transferred to the vertical charge coupled device region 22 through the surface channel of the p-type well 16 which provides the transmission gate region. Because the photoelectric conversion region 18 extends to the bottom edge of the gate electrode layer 26, the boundary between the silicon and the gate insulation layer is depleted and a boundary state is thus activated. A relatively large current can thus be generated. To reduce an after image, a thermal process can be used when forming the photoelectric conversion region 18 so as to be self-aligned with the gate electrode layer 26. The previously formed p-type well 16 and vertical charge coupled region 22, however, may be influenced by this thermal process, and it may thus be difficult to form a shallow junction. The capacitance per unit area may thus be reduced, and the maximum charge handling capability may also be reduced. Because there is a wide depletion region under the channel, the image smear may increase.
A method for reducing the disadvantages discussed above is discussed in the reference by Ozaki et al. entitled "High-Packing Pixel With Punchthrough Read-Out Method For An HDTV Interline CCD" (IEEE Trans. Electron Devices, Vol. 41, No. 7, July 1994, pp. 1128-1135), and illustrated in FIG. 2. As shown in FIG. 2, a p-type well 42 having a relatively low dopant concentration is formed in an n-type substrate 40 also having a relatively low dopant concentration. An n-type well 44 having a relatively low dopant concentration is formed on the p-type well 42, and an n-type well 46 having an intermediate dopant concentration is formed on the n-type well 44. An n-type photoelectric conversion region 48 is formed on the n-type well 46 at the light receiving region of the pixel.
A masking pattern defines a width L1 of a transmission gate region and a width L2 of a channel stop region. A p-type well 50 having an intermediate dopant concentration and an n-type vertical charge coupled region 54 having a relatively high dopant concentration are sequentially formed around the surface of the substrate through the masking pattern. A gate isolation layer 56 is deposited on the surface of the substrate, and a gate electrode layer 58 is then formed. A p-type hole accumulation layer 52 having a relatively high dopant concentration is formed, and this p-type hole accumulation layer 52 is self-aligned with the gate electrode layer 58. An insulation layer 60 is formed on the gate electrode layer 58, and a light shielding layer 62 is formed on the insulation layer 60.
The solid state imaging device having the punch through readout structure illustrated in FIG. 2 may, however, have shortcomings. First, the p-type well 50 around the vertical charge coupled device should be shallow to facilitate the signal transmission to the vertical charge coupled device 54 from the photoelectric conversion region 48. If a high voltage is applied to the substrate 40 to drive an electric shutter, however, the signal charge may be influenced because the charge which is being transmitted to the vertical charge coupled device flows to the substrate.
Second, it may difficult to uniformly adjust the thermal diffusion process used after the ion implantation when forming the p-type well 50. When forming the mask pattern which defines the width L1 of the transmission gate region and the width L2 of the channel stop region, a characteristic variation may occur due to misalignment. Third, if the width L2 of a channel stop region is not stably adjusted, the charge accumulated in the photoelectric conversion region horizontally adjacent to the vertical charge coupled device may flow to the vertical charge coupled device during a field shift such as during a readout. Fourth, because the aperture ratio of the pixel region is reduced as much as the transmission gate region, the sensitivity may be lowered.